1. Field of the Invention
The present invention relates to electronics and, more specifically but not exclusively, to clock and data recovery (CDR) circuits.
2. Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
In a digital communication system in which symbols representing modulated, encoded user data are transmitted as an analog signal from a transmitter to a receiver, the receiver may have clock-and-data recovery (CDR) circuitry that (i) derives a recovered clock signal from level transitions in the received analog signal and (ii) uses the recovered clock signal to sample the analog signal to generate a sampled binary data signal that is then demodulated and decoded to recover the original user data.
In order to accurately recover the original user data, it is important to sample the analog signal near the middle of the unit intervals (UIs) corresponding to the bits represented in the analog signal to avoid ambiguities associated with sampling the analog signal near the signal level transitions. This desired sampling is achieved by controlling the phase of the recovered clock signal relative to the analog signal.
Conventional CDR circuits have phase-adjustment circuitry that accurately controls the phase of the recovered clock signal after the phase has been initially set near the middle of the unit intervals. However, if the initial phase is not set sufficiently near the middle of the unit intervals, then the phase-adjustment circuitry might not function as desired.